|
In electronic low power digital synchronous circuit design, operand isolation is a technique for minimizing the energy overhead associated with redundant operations by selectively blocking the propagation of switching activity through the circuit.〔 ("Overview of the power minimization techniques employed in the IBM PowerPC 4xx embedded controllers" ) 〕 This technique isolates sections of the circuit (operation) from "seeing" changes on their inputs (operands) unless they are expected to respond to them. This is usually done using latches at the inputs of the circuit. The latches become transparent only when the result of the operation is going to be used. One can also use multiplexers or simple AND gates instead of latches. ==Overhead== There is some area overhead associated with this technique since the circuit designer needs to add extra circuitry, i.e. latches, at the inputs. Also, if the latches are being added in a pipeline stage, they might change the critical path, and hence increase the cycle time. In cases where the overhead is not acceptable, one can think of clock gating as an alternative method of low power design. 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「Operand isolation」の詳細全文を読む スポンサード リンク
|